Parallel bit interleaver

ABSTRACT

A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

TECHNICAL FIELD

The present disclosure relates to the field of digital communications,and more specifically to a bit interleaver for a bit-interleaved codingand modulation system with quasi-cyclic low-density parity-check codes.

BACKGROUND ART

In recent years, bit-interleaved coding and modulation (hereinafter,BICM) systems have been used in the field of digital communications(see, for example, Non-Patent Literature 1).

BICM systems generally incorporate the following three steps.

(1) Encoding data blocks into codewords using, for example, quasi-cycliclow-density parity check (hereinafter, QC LDPC) code or similar.

(2) Performing bit interleaving on the bits of each codeword.

(3) Dividing each bit interleaved codeword into constellation wordshaving a number of constellation bits, and mapping the constellationwords to constellations.

CITATION LIST Patent Literature

[Patent Literature 1]

ETSI EN 302 755 V1.2.1 (DVB-T2 standards)

SUMMARY OF INVENTION Technical Problem

Typically, efficiency is desirable in interleaving applied to thecodewords of quasi-cyclic low-density parity-check codes.

The present disclosure aims to provide an interleaving method enablingefficient interleaving to be applied to the codewords of quasi-cycliclow-density parity-check codes.

Solution to Problem

In order to achieve the above-stated aim, a bit interleaving method fora communication system using quasi-cyclic low-density parity check codescomprises: a reception step of receiving a codeword of the quasi-cycliclow-density parity check codes made up of N cyclic blocks each includingQ bits; a bit permutation step of applying a bit permutation process tothe codeword so as to permute the bits in the codeword; and a divisionstep of dividing the codeword, after the bit permutation process, into aplurality of constellation words, each of the constellation words beingmade up of M bits and indicating one of 2^(M) constellation points in apredetermined constellation, wherein prior to the bit permutationprocess, the codeword is divided into F×N/M folding sections, F being aninteger greater than one, each of the folding sections including M/F ofthe cyclic blocks, and each of the constellation words being associatedwith one of the F×N/M folding sections, and in the bit permutation step,the bit permutation process is applied such that the M bits in each ofthe constellation words include F bits from each of M/F different cyclicblocks in a given folding section associated with a given constellationword, and such that all bits in the given folding section are mapped toonly Q/F of the constellation words associated with the given foldingsection.

Advantageous Effects of Invention

The bit interleaving method of the present invention enables effectiveinterleaving to be applied to the codewords of the quasi-cycliclow-density parity-check codes.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram showing the configuration of a transmitterthat includes a typical BICM encoder.

FIG. 2 illustrates an example of a parity-check matrix for quasi-cycliclow-density parity check codes having a coding rate of 1/2.

FIG. 3 illustrates an example of a parity-check matrix forrepeat-accumulate quasi-cyclic low-density parity check codes having acoding rate of 2/3.

FIG. 4 illustrates a parity-check matrix for the repeat-accumulatequasi-cyclic low-density parity check codes of FIG. 3 after a rowpermutation.

FIG. 5 illustrates a parity-check matrix for the repeat-accumulatequasi-cyclic low-density parity check codes of FIG. 3 after a rowpermutation and a parity permutation.

FIG. 6 describes different robustness levels of the bits encoded ineight PAM symbols.

FIG. 7 is a block diagram showing the configuration of a typical bitinterleaver where the cyclic factor Q is 8, the number of cyclic blocksper low-density parity check codeword N is 12, and the number of bitsper constellation M is 4.

FIG. 8A is a block diagram showing the configuration of a DVB-T2modulator used in the DVB-T2 standard, and FIG. 8B is a block diagramshowing the configuration of a BICM encoder for the DVB-T2 modulator ofFIG. 8A.

FIG. 9A illustrates a write process for the bits of a 16K codeword(i.e., an LDPC code where the LDPC codeword length is 16200 bits) asperformed by a column-row interleaver having twelve columns, and FIG. 9Billustrates a read process for the bits of the codeword written in themanner indicated by FIG. 9A as performed by the column-row interleaver.

FIG. 10A illustrates a write process for the bits of a 16K codeword asperformed by a column-row interleaver having eight columns, and FIG. 10Billustrates a read process for the bits of the codeword written in themanner indicated by FIG. 10A as performed by the column-row interleaver.

FIG. 11 is a block diagram showing the configuration of a bit-to-celldemultiplexer used for 16K codes of 16-QAM in the DVB-T2 standard.

FIG. 12 is a block diagram showing the configuration of a bit-to-celldemultiplexer used for 16K codes of 64-QAM in the DVB-T2 standard.

FIG. 13 is a block diagram showing the configuration of a bit-to-celldemultiplexer used for 16K codes of 256-QAM in the DVB-T2 standard.

FIG. 14 illustrates a problem occurring for 16K codes with aneight-column DVB-T2 bit interleaver.

FIG. 15 illustrates a problem occurring for 16K codes with atwelve-column DVB-T2 bit interleaver.

FIG. 16 illustrates a problem occurring for 16K codes with aneight-column DVB-T2 bit interleaver when column twisting is applied.

FIG. 17 illustrates a problem occurring for 16K codes with atwelve-column DVB-T2 bit interleaver when column twisting is applied.

FIGS. 18A and 18B respectively illustrate a first and second conditiondiscovered by the inventors enabling an extremely effective interleaverto be provided.

FIG. 19 illustrates a mapping function by an interleaver pertaining toan Embodiment.

FIG. 20 is a block diagram showing the configuration of an interleaverpertaining to an Embodiment.

FIG. 21A is a block diagram showing the configuration of a sectionpermutator performing the section permutation illustrated in FIG. 20,and FIG. 21B illustrates a mapping function of the section permutatorshown in FIG. 21A.

FIG. 22A is a block diagram showing an alternate configuration of asection permutator performing the section permutation illustrated inFIG. 20, and FIG. 22B illustrates a mapping function of the sectionpermutator shown in FIG. 22A.

FIG. 23 is a block diagram showing the configuration of an interleaverpertaining to another Embodiment.

FIG. 24 is a block diagram showing the configuration of the bitinterleaver shown in FIG. 23.

FIG. 25 is a block diagram showing the configuration of a transmitterpertaining to a further Embodiment.

FIG. 26 is a block diagram showing the configuration of a BICM encoderpertaining to a further Embodiment.

FIG. 27 is a block diagram showing the configuration of a receiverincluding a non-iterative BICM decoder, pertaining to a furtherEmbodiment.

FIG. 28 is a block diagram showing the configuration of a receiverincluding an iterative BICM decoder, pertaining to a further Embodiment.

FIG. 29 is a block diagram showing the configuration of an iterativeBICM decoder pertaining to a further Embodiment.

FIG. 30 illustrates an example of cyclic blocks included in and excludedfrom a parallel interleaver process.

FIGS. 31A and 31B respectively illustrate a first and second conditiondiscovered by the inventors enabling an extremely effective interleaverto be provided.

FIG. 32 is a block diagram showing the configuration of an interleaverpertaining to another Embodiment.

FIG. 33A illustrates a mapping function for a situation without folding(F=1), and FIG. 33B illustrates a mapping function for a situation withfolding (F=2).

FIG. 34A is a block diagram showing the configuration of a (folding)section permutator for the situation without folding (F=1), and FIG. 34Bis a block diagram showing the configuration of a folding sectionpermutator for the situation with folding (F=2).

FIG. 35 is a block diagram showing the configuration of an interleaverpertaining to another Embodiment.

FIG. 36 is a block diagram showing the configuration of the bitinterleaver shown in FIG. 35.

FIG. 37 is a block diagram showing the configuration of a transmitterpertaining to a further Embodiment.

FIG. 38 is a block diagram of a receiver including a non-iterative BICMdecoder, pertaining to a further Embodiment.

FIG. 39 is a block diagram of a receiver including an iterative BICMdecoder, pertaining to a further Embodiment.

FIG. 40 illustrates LLR memory locations for folding with F=2, and bitpositions for the first constellation word.

FIG. 41 schematically represents mapping of constellation blockspertaining to hybrid QPSK+16QAM codes.

FIG. 42 is a block diagram showing the configuration of an interleaverpertaining to another Embodiment.

FIG. 43 is a block diagram showing the configuration of an interleaverpertaining to another Embodiment.

DESCRIPTION OF EMBODIMENTS Background Information

FIG. 1 is a block diagram showing the configuration of a transmitter 100that includes a typical bit-interleaved coding and modulation(hereinafter, BICM) encoder. As shown, the transmitter 100 includes aninput processor 110, a BICM encoder (in turn including a low-densityparity check (hereinafter, LDPC) encoder 120, a bit interleaver 130, anda constellation mapper 140), and a modulator 150.

The input processor 110 converts an input bitstream into blocks of apredetermined length. The LDPC encoder 120 encodes the blocks intocodewords using LDPC codes, and then transmits the codewords to the bitinterleaver 130. The bit interleaver 130 applies an interleaving processto each LDPC codeword, then divides each interleaved codeword into asequence of cell words (i.e., constellation words). The constellationmapper 140 maps each cell word (i.e., constellation word) to a sequenceof constellations (e.g., using QAM). The generic modulator 150 at theoutput includes all processing blocks from the output of the BICMencoder to a radio frequency (hereinafter, RF) power amplifier.

An LDPC code is a linear error correcting code that is fully defined bya parity-check matrix (hereinafter, PCM). A PCM is a binary sparsematrix that represents the connection of codeword bits (hereinafter alsotermed variable nodes) to the parity checks (hereinafter also termedcheck nodes). The columns and the rows of the PCM respectivelycorrespond to the variable nodes and the check nodes. In the PCM, aconnection between a variable node and a check node is represented by aone-element.

Quasi-cyclic low-density parity check (hereinafter, QC LDPC) codes areone variety of LDPC codes. QC LDPC codes have a structure that isparticularly suited to hardware implementation. In fact, most standardsin use today employ QC LDPC codes. The PCM of a QC LDPC code has aspecial configuration made up of a plurality of circulant matrices. Acirculant matrix is a square matrix in which each row is a cyclic shiftof the elements in the previous row, and has one, two, or more foldeddiagonals. Each circulant matrix has a size of Q×Q. Here, Q representsthe cyclic factor of the QC LDPC. The above-described quasi-cyclicconfiguration allows Q check nodes to be processed in parallel, which isclearly beneficial for efficient hardware implementation.

FIG. 2 shows the PCM of a QC LDPC code having a cyclic factor Q ofeight, as an example. In FIG. 2, as well as in later-described FIGS. 3and 5, the smallest squares each represent one element of the PCM, wherethe black squares are one-elements and all other squares arezero-elements. The PCM shown has circulant matrices with one or twofolded diagonals apiece. This QC LDPC code encodes a block of 8×6=48bits into a codeword of 8×12=96 bits. Accordingly, the coding rate ofthe QC LDPC is 48/96=1/2. The codeword bits are divided into a pluralityof blocks of Q bits each. The Q bit blocks are hereinafter termed cyclicblocks (or cyclic groups) for this relation to the cyclic factor of Q.

A special variety of QC LDPC codes are repeat-accumulate quasi-cycliclow-density parity check (hereinafter, RA QC LDPC) codes. RA QC LDPCcodes are well known as being easy to encode, and are therefore used ina wide variety of standards (e.g., in second-generation DVB standards,including DVB-S2, DVB-T2, and DVB-C2). The right-hand side of the PCMcorresponds to the parity bits. The one-elements therein are arranged ina staircase structure. FIG. 3 shows an example of a PCM for a RA QC LDPChaving a coding rate of 2/3.

Above, and throughout, DVB-T is an abbreviation of Digital VideoBroadcasting-Terrestrial, DVB-S2 is an abbreviation of Digital VideoBroadcasting-Second Generation Satellite, DVB-T2 is an abbreviation ofDigital Video Broadcasting-Second Generation Terrestrial, and DVB-C2 isan abbreviation of Digital Video Broadcasting-Second Generation Cable.

By applying a simple row permutation to the PCM shown in FIG. 3, thequasi-cyclic structure of the RA QC LDPC codes is revealed, with theexception of the parity portion, shown in FIG. 4. The row permutation isa simple change of the graphical representation having no influence onthe code definition.

The quasi-cyclic structure of the PCM parity portion is imparted byapplying a suitable row permutation to only the parity bits of the PCMshown in FIG. 4. This technique is widely known in the field and is usedin standards such as DVB-T2, under the name of parity interleaving or ofparity permutation. FIG. 5 shows the PCM obtained as a result ofapplying such parity permutation to the PCM shown in FIG. 4.

Typically, the bits of an LDPC codeword vary in importance, and the bitsof a constellation vary in robustness level. Mapping the bits of an LDPCcodeword to a constellation directly, i.e., without interleaving, leadsto suboptimal performance. Thus, the bits of the LDPC codeword requireinterleaving prior to mapping onto constellations.

For this purpose, the bit interleaver 130 is provided between the LDPCencoder 120 and the constellation mapper 140, as shown in FIG. 1. Bycarefully designing the bit interleaver 130, the association between thebits of the LDPC codeword and the bits encoded by the constellation isimproved, leading to improved receiver performance. Performance istypically measured using the bit-error rate (hereinafter, BER) as afunction of the signal-to-noise ratio (hereinafter, SNR).

The bits of the LDPC codeword differ in importance primarily because notall bits are necessarily involved in the same number of parity checks.The more parity checks (check nodes) a given codeword bit (variablenode) is involved in, the more important the given codeword bit is in aniterative LDPC decoding process. A further reason is that the variablenodes each have different connectivity to the cycles of a Tanner graphrepresenting the LDPC codes. Therefore, the codeword bits are likely todiffer in importance despite being involved in the same number of paritychecks. These ideas are well understood in the field. As a rule, theimportance of the variable nodes increases as the number of check nodesconnected therewith increases.

In the particular case of QC LDPC codes, all bits included in a cyclicblock of Q bits have the same number of parity checks applied thereto,and have the same connectivity to the cycles of the Tanner graph. Thus,all bits have the same importance.

Similarly, the encoded bits of a constellation are widely known to havedifferent levels of robustness. For example, a quadrature amplitudemodulation (hereinafter, QAM) constellation is made up of twoindependent pulse amplitude modulation (hereinafter, PAM) symbols, onesymbol corresponding to the real part and the other symbol correspondingto the imaginary part. The two PAM symbols each encode M bits. FIG. 6shows 8-PAM symbols using Gray encoding. As shown, the bits encoded byin each PAM symbol vary in terms of level of robustness. The differencein robustness is a result of the distance between two subsets defined byeach bit (e.g., 0 or 1) being different for each of the bits. Thegreater the distance, the more robust and reliable the bit. FIG. 6indicates that bit b3 has the highest robustness level, while bit b1 hasthe lowest robustness level.

Thus, a 16-QAM constellation encodes four bits and has two robustnesslevels. Also, a 64-QAM constellation encodes six bits and has threerobustness levels. Likewise, a 256-QAM constellation encodes eight bitsand has four robustness levels.

The following parameters are hereinafter used throughout the presentdescription.

Cyclic factor: Q=8

Number of cyclic blocks per LDPC codeword: N=12

Number of bits per constellation: M=4 (i.e., 16-QAM)

Given the above parameters, the number of constellations to which eachLDPC codeword is mapped is equal to Q×N/M=24. Typically, the parametersQ and N are selected such that Q×N is equal to a multiple of M for allconstellations supported by the system.

FIG. 7 is a block diagram showing the configuration of a typicalinterleaver when the above parameters are applied. In FIG. 7, the 12cyclic blocks are labeled QB1, QB 12, and the 24 constellations arelabeled C1, . . . , C24. A bit interleaver 710 interleaves the 96 bitsof the LDPC codeword.

A conventional bit interleaver is known from the DVB-T2 standard (seeETSI EN 302 755). The DVB-T2 standard is a television standardpresenting improvements over the DVB-T standard, and describes asecond-generation baseline transmission system for digital televisionbroadcasting. The DVB-T2 standard gives the details of a channel codingand modulation system for broadcast television services and genericdata.

FIG. 8A is a block diagram showing the structure of a modulator used inthe DVB-T2 standard (i.e., a DVB-T2 modulator). The DVB-T2 modulator 800includes an input processor 810, a BICM encoder 820, a frame builder830, and an OFDM generator 840.

The input processor 810 converts an input bitstream into blocks of apredetermined length. The BICM encoder 820 applies BICM processing tothe input. The frame builder 830 uses input from the BICM encoder 820and the like to generate a distribution frame structure in the DVB-T2format. The OFDM generator 840 performs pilot addition, fast Fouriertransform application, guard interval insertion, and the like on thedistribution frame structure, then outputs a transmission signal in theDVB-T2 format.

The BICM used in the DVB-T2 standard is described in chapter 6 of theETSI EN 302 755 standard. The aforementioned standard is incorporatedherein by reference and explained below.

FIG. 8B is a block diagram showing the structure of the BICM encoder 820in the DVB-T2 modulator 800 illustrated in FIG. 8A. FIG. 8B omits outerBCH encoding, constellation rotation, the cell interleaver, the timeinterleaver, and the like.

The BICM encoder 820 includes an LDPC encoder 821, a bit interleaver (inturn including a parity interleaver 822 and a column-row interleaver823), a bit-to-cell demultiplexer 824, and a QAM mapper 825.

The LDPC encoder 821 encodes the blocks into codewords using LDPC codes.The bit interleaver (which includes the parity interleaver 822 and thecolumn-row interleaver 823) performs interleaving on the bits of thecodewords. The bit-to-cell demultiplexer 824 demultiplexes theinterleaved bits of the codewords into cell words (constellation words).

The QAM mapper 825 maps the cell words (constellation words) to complexQAM symbols. The complex QAM symbols are also termed cells. In fact, thebit-to-cell demultiplexer 824 may also be considered a part of the bitinterleaver. In such situations, the BICM encoder conforming to theDVB-T2 standard may be considered to have the basic structure shown inFIG. 1.

The LDPC codes used in the DVB-T2 standard are RA QC LDPC codes having acyclic factor of Q=360. Two codeword lengths are defined for the DVB-T2standard, one being 16200 bits and the other being 64800 bits. In thepresent document, LDPC codes using a codeword length of 16200 bits arereferred to as 16K codes (or as 16K LDPC codes), and LDPC codes having acodeword length of 64800 bits are referred to as 64K codes (or as 64KLDPC codes). The number of cyclic blocks per codeword is 45 for the 16Kcodes and 180 for the 64K codes. The available codes corresponding toeach block length (codeword length) are given in Tables A1 through A6 ofETSI EN 302 755 for the DVB-T2 standard.

The bit interleaver is used only for constellations larger thanquadrature phase-shift keying constellations (hereinafter, QPSK), andincludes the parity interleaver 822, the column-row interleaver 823, andthe bit-to-cell demultiplexer 824. According to the DVB-T2 standard, thebit interleaver does not include the bit-to-cell demultiplexer 824.However, the present document pertains to interleaving as applied toLDPC codes prior to constellation mapping. As such, the bit-to-celldemultiplexer 824 is treated as a part of the bit interleaver.

The parity interleaver 822 performs parity permutation on the paritybits of each codeword so as to clarify the quasi-cyclic structurethereof, as described above (see FIGS. 4 and 5).

Conceptually, the column-row interleaver 823 operates by writing thebits of each LDPC codeword column-wise in an interleaver matrix, thenreading the bits row-wise. The first bit of the LDPC codeword is writtenfirst, and is read first. After writing and before reading the LDPCcodeword bits, the column-row interleaver 823 cyclically shifts thecolumns of bits by a predetermined number of positions. This is termedcolumn twisting in the DVB-T2 standard. The number of columns Nc and thenumber of rows Nr in the interleaver matrix are given in Table 1 forseveral constellation sizes, according to the two aforementioned LDPCcodeword lengths.

TABLE 1 LDPC No. codeword length Constellation size of columns: Nc No.of rows: Nr 16200 16-QAM 8 2025 64-QAM 12 1350 256-QAM  8 2025 6480016-QAM 8 8100 64-QAM 12 5400 256-QAM  16 4050

The number of columns Nc is twice the number of bits per constellation,with the exception of 16K codes with a 256-QAM constellation. Thisexception occurs because the LDPC codeword length of 16200 is not amultiple of 16, i.e., is not twice the number of bits per 256-QAMconstellation.

The codeword bit writing process and bit reading process for 16K codesperformed by the column-row interleaver 823 is illustrated in FIGS. 9Aand 9B for twelve columns, and in FIGS. 10A and 10B for eight columns.Each of the small squares corresponds to one bit of the LDPC codeword.The blackened square represents the first bit of the LDPC codeword. Thearrows indicate the order in which the bits are written to and read fromthe interleaver matrix. For example, when the interleaver matrix hastwelve columns, the codeword bits of the 16K code are written in theorder given in FIG. 9A, namely (Row 1, Column 1), (Row 2, Column 1), . .. , (Row 1350, Column 1), (Row 1, Column 2), . . . , (Row 1350, Column12), then read in the order given in FIG. 9B, namely (Row 1, Column 1),(Row 1, Column 2), . . . , (Row 1, Column 12), (Row 2, Column 1), . . ., (Row 1350, Column 12). FIGS. 9A, 9B, 10A, and 10B do not illustratethe column twisting process.

Prior to QAM mapping, the bit-to-cell demultiplexer 824 demultiplexesthe LDPC codewords to obtain a plurality of parallel bit streams. Thenumber of streams is twice the number of encoded bits M per QAMconstellation, i.e., 2×M, with the exception of 16K LDPC codes with a256-QAM constellation. For 16K LDPC codes with a 256-QAM constellation,the number of streams equal to the number of encoded bits M per QAMconstellation. The M encoded bits per constellation are referred to asone cell word (constellation word). For the 16K LDPC codes, the numberof cell words per codeword is 16200/M, as given below.

8100 cells for QPSK,

4050 cells for 16-QAM,

2700 cells for 64-QAM, and

2025 cells for 256-QAM.

According to Table 1, given above, the number of parallel streams isequal to the number of columns in the column-row interleaver forconstellations larger than QPSK. The bit-to-cell demultiplexerscorresponding to 16-QAM constellations, 64-QAM constellations, and256-QAM constellations for 16K LDPC codes are respectively shown inFIGS. 11, 12, and 13. The bit notation used is that of the DVB-T2standard.

As shown in FIG. 11 (and FIGS. 12 and 13), the bit-to-cell demultiplexer824 includes a simple demultiplexer 1110 (also 1210, 1310) and a demuxpermutator 1120 (also 1220, 1320).

In addition to having the simple demultiplexer 1110 (1210, 1310) simplydemultiplex the LDPC codewords, to which interleaving has been applied,the bit-to-cell demultiplexer 824 also has the demux permutator 1120(1220, 1320) perform a permutation on the demultiplexed parallel bitstreams.

However, when the column-row interleaver is used (i.e., for 16-QAMconstellations or larger), the permutation applied to the bit streams isidentical to a permutation applied to the columns of the column-rowinterleaver due to the number of parallel bit streams being equal to thenumber of columns. Therefore, the permutation performed by thebit-to-cell demultiplexer 824 is regarded as a part of the bitinterleaver.

The bit interleaver used in the DVB-T2 standard essentially has twoproblems.

The first problem is that parallelism is impaired when the number ofcyclic blocks in the LDPC codeword is not a multiple of the number ofcolumns in the bit interleaver matrix. Reduced parallelism leads toincreased latency. This is especially problematic when iterative BICMdecoding is used by the receiver. This situation occurs for severalcombinations of LDPC codeword length and constellation size in theDVB-T2 standard.

FIGS. 14 and 15 illustrate the aforementioned situation for 16K LDPCcode cases where the interleaver matrix has eight and twelve columns,respectively. Eight columns are used in the interleaver matrix for16-QAM constellations and 256-QAM constellations. Twelve columns areused in the interleaver matrix for 64-QAM constellations. In FIGS. 14and 15, the grid represents an LDPC codeword, the small squares eachrepresent one bit of the LDPC codeword, the rows correspond to thecyclic blocks, and the columns correspond to bits of the same bit indexwithin a cyclic block. The blackened squares represent eighth andtwelfth bits of the first row in the interleaver matrix. For ease ofcomprehension, the number of bits per cyclic block has been reduced from360 to 72. However, this does not affect the understanding.

The second problem is that, in the DVB-T2 standard, the number ofpossible bit interleaver configurations is limited by the number ofcolumns in the bit interleaver matrix.

A further problem of the DVB-T2 bit interleaver is that the regularityand parallelism of the permutation is impaired by the column twistingprocess. FIGS. 16 and 17 respectively illustrate the same situations asFIGS. 14 and 15, with the addition of the column twisting process. Whenthe interleaver matrix has eight columns for the 16K LDPC codes, thecolumn twisting values for the columns of the DVB-T2 bit interleaver are(0, 0, 0, 1, 7, 20, 20, 21). Similarly, when the interleaver matrix hastwelve columns for the 16K LDPC codes, the column twisting values forthe columns of the DVB-T2 bit interleaver are (0, 0, 0, 2, 2, 2, 3, 3,3, 6, 7, 7).

Accordingly, a bit interleaver that reduces latency while improvingparallelism is desired. These properties are particularly important initerative BICM decoding.

(Experimenter Discoveries)

The inventor has discovered, as the fruit of prolonged experimentation,that an interleaver satisfying the following two conditions is extremelyefficient.

(Condition 1)

The M bits of each constellation are each mapped to one of M differentcyclic blocks of the LDPC codeword. This is equivalent to mapping onebit from M different—of the LDPC codeword to a constellation word. Thisis schematically illustrated in FIG. 18A.

(Condition 2)

All constellation words mapped to the M cyclic blocks are mapped only tothat particular cyclic block. This is equivalent to mapping all M×Q bitsof the M different cyclic blocks each made up of Q bits to exactly Qconstellations. This is schematically illustrated in FIG. 18B.

The above conditions imply that exactly Q constellations are mapped toeach set of M cyclic blocks.

Embodiment 1

The following describes the details of a bit interleaver (i.e., aparallel bit interleaver) that satisfies conditions 1 and 2 given above.In the following description, processing and the units performing suchprocessing are labeled with the same reference numbers whereverapplicable.

In the present document, each group of M cyclic blocks and each group ofQ constellation words is referred to as a section (or as an interleaversection).

FIGS. 19 and 20 are block diagrams respectively illustrating the mappingfunction of a bit interleaver satisfying Conditions 1 and 2 andcorresponding to the aforementioned parameters (i.e., Q=8, M=4, N=12),and a sample configuration for such a bit interleaver.

In FIGS. 19 and 20, the QC-LDPC codewords are made up of N=12 cyclicblock, each in turn made up of Q=8 bits. Each of the 24 constellationwords is made up of M=4 bits. Each constellation word indicates one of2^(M)=16 constellation points. The bit interleaver is divided into N/M=3sections. The 24 constellation words are each associated one of thethree sections.

A bit interleaver 2000 includes a bit permutator 2010, which in turnincludes N/M (=3) section permutators 2021, 2022, and 2023, eachoperating independently. However, rather than providing three sectionpermutators, a single section permutator may, for example, be providedso as to perform the three section permutation processes describedbelow, switching therebetween over time.

The section permutators (2021, 2022, and 2023) each independentlyperform a section permutation on the 32 bits making up each of 4 cyclicblocks, such that one bit from every four cyclic blocks (i.e., QB1through QB4, QB5 through QB8, and QB9 through QB12) is mapped to eachgroup of eight constellation words (i.e., C1 through C8, C9 through C16,and C17 through C24).

Conditions 1 and 2, described above, ensure that the bit interleaver isdivisible into N/M parallel sections. The section permutations appliedto the parallel sections may all apply the same permutation rules, mayeach apply different permutation rules, or may involve a subset of thesections applying identical permutation rules while other differ.

For example, the section permutators may map the Q bits of a cyclicblock (which each have the same importance in LDPC decoding) to bitshaving the same bit index (i.e., having the same robustness level) inthe Q constellation words. For each cyclic block, the Q bits may be insequential or in permutated order. The latter case is described withreference to FIGS. 21A and 21B, while the former case is described withreference to FIGS. 22A and 22B.

FIG. 21A structurally illustrates the section permutator of FIG. 20.

The section permutator 2101 includes intra-cyclic-block permutators 2111through 2114 and a column-row permutator 2131. Rather than providingfour intra-cyclic-block permutators, for example, a singleintra-cyclic-block permutator may be provided and perform the fourintra-cyclic-block permutation processes, described later, switchingtherebetween over time.

The intra-cyclic-block permutators (2111-2114) each perform anintra-cyclic-block permutation on the Q-bit (8-bit) cyclic blocks(QB1-QB4). The intra-cyclic-block permutations applied to the cyclicblocks in each section may all apply the same permutation rules, mayeach apply different permutation rules, or may involve a subset of thesections applying identical permutation rules while other differ.

The column-row permutator 2131 performs a column-row permutation on eachgroup of M×Q (=32) bits. Specifically, the column-row permutator 2131writes the M×Q bits row-wise into a M×Q (8×4) matrix, then reads the M×Qbits column-wise therefrom, thus applying the column-row permutation.The column-row permutation applied by the column-row permutator 2131resembles the permutation applied to the 12×1350 matrix shown in FIGS.9A and 9B, where Q columns and M rows are used, the writing processoccurs column-wise, and the reading process occurs row-wise.

FIG. 21B is a structural representation of the section permutator shownin FIG. 21A. In FIG. 21B, the constellation words of M=4 bits are eachdenoted b1 through b4.

However, a variation in which the intra-cyclic-block permutation processis not part of the section permutation process is also plausible.

For example, a section permutation implemented without executing theintra-cyclic-block permutation and a structure of mapping by the sectionpermutator are shown in FIGS. 22A and 22B. The section permutator 2201includes a column-row permutator 2131 and performs a simple column-rowpermutation. In FIG. 22B, the constellation words of M=4 bits are eachdenoted b1 through b4.

The section permutation described in FIGS. 21A, 21B, 22A and 22B may beapplied to cyclic blocks QB5-QB8 and QB9-QB12.

Advantageously, an additional cyclic block permutation may be applied tothe N cyclic blocks before the bit interleaver performs the sectionpermutation. FIG. 23 is a structural diagram of the additional cyclicblock permutation applied by the bit interleaver. In this context, thecyclic block permutation plays a role similar to that of the permutationperformed by the bit-to-cell demultiplexer in the DVB-T2 standard.

The bit interleaver 2300 shown in FIG. 23 includes a cyclic blockpermutator 2310 and a bit permutator 2010 (which in turn includessection permutators 2021-2023).

The cyclic block permutator 2310 performs cyclic block permutations2311-2318 on the cyclic blocks QB1-QB12. Here, the cyclic blockpermutations 2311-2318 all follow the same permutation rules.

The cyclic block permutation performed on the N cyclic blocks isparticularly advantageous in enabling optimized mapping of the LDPCcodeword bits onto the constellation bits, resulting in optimizedperformance.

FIG. 24 is a schematic block diagram of the bit interleaver 2300 shownin FIG. 23. The bit interleaver 2400 shown in FIG. 24 includes threestages, A, B, and C.

Stage A: (inter) cyclic block permutation

Stage B: intra-cyclic-block permutation

Stage C: column-row permutation

The (inter) cyclic block permutation is applied to the N cyclic blocksmaking up the codeword, the intra-cyclic-block permutation is applied tothe Q bits of each cyclic block, and the column-row permutation isapplied to the M×Q sections.

The bit interleaver 2400 shown in FIG. 24 includes the cyclic blockpermutator 2310 and the bit permutator 2010 (which in turn includes thesection permutators 2101-2103). The section permutator 2101 (2102, 2013)includes the intra-cyclic-block permutators 2111-2114(2115-2118,2119-2122) and the column-row permutator 2131 (2132, 2133).

In the bit interleaver 2400, the (inter) cyclic block permutation isperformed by the cyclic block permutator 2310 (stage A), theintra-cyclic-block permutation is performed by the intra-cyclic-blockpermutators 2111-2122 (stage B), and the column-row permutation isperformed by the column-row permutators 2131-2133 (stage C).

The intra-cyclic-block permutators 2111-2122 may be removed from the bitinterleaver 2400 shown in FIG. 24, such that the bit interleaver isconfigured not to perform the intra-cyclic-block permutation. Also, thebit interleaver 2400 may perform the (inter) cyclic block permutationbefore the intra-cyclic-block permutation rather than after theintra-cyclic-block permutation, or may perform the (inter) cyclic blockpermutation before and after the intra-cyclic-block permutation.

The intra-cyclic-block permutators may have similar structures. This isadvantageous in that the intra-cyclic-block permutators are thusimplementable using identical resources (e.g., hardware blocks).Alternatively, the intra-cyclic-block permutations may consist ofcyclical shifts, which allow for efficient hardware implementation usingbarrel shifters. An implementation using the barrel shifters in the LDPCdecoder is also possible.

The following describes a transmitter that includes the bit interleaverperforming a bit interleaving process that satisfies Conditions 1 and 2,with reference to FIG. 25.

FIG. 25 is a block diagram of a transmitter pertaining to a furtherEmbodiment of the present disclosure. As shown in FIG. 25, a transmitter2500 includes a BICM encoder (which in turn includes an LDPC encoder2510, a bit interleaver 2520, and a constellation mapper 2530) and amodulator 2540.

The LDPC encoder 2510 encodes input blocks into codewords using QC-LDPCcodes, and then transmits the codewords to the bit interleaver 2520.

The bit interleaver 2520 receives the codeword in QC-LDPC code from theLDPC encoder 2510. The codeword is made up of N=12 cyclic blocks, eachcyclic block including Q=8 bits. The bit interleaver 2520 performsinterleaving on the bits of the codewords so as to permute the bits ofeach of the codewords. The bit interleaver 2520 divides the interleavedcodeword into a plurality of constellation words, each made up of M=4bits and indicating one of 2^(M)=16 constellation points, then outputsthe constellation words to the constellation mapper 2530. The bitinterleaver 2520 may apply the bit interleaving process discussed withreference to FIGS. 19 through 22A and 22B, or may apply a variant bitpermutation process. Also, the bit interleaver 2520 may apply anadditional cyclic block permutation process, such as the processdiscussed with reference to FIGS. 23 and 24 or a variation thereof.

The constellation mapper 2530 receives the constellation words from thebit interleaver 2520 and performs constellation mapping on theconstellation words so received.

The modulator 2740 generates a transmission signal using orthogonalfrequency division multiplexing (hereinafter, OFDM) or similar.

The following describes a BICM encoder that includes the bit interleaverperforming a bit interleaving process that satisfies Conditions 1 and 2,with reference to FIG. 26.

FIG. 26 is a block diagram of an example BICM encoder pertaining to afurther Embodiment of the disclosure. In FIG. 26, the BICM encoder 2600corresponds to the above-given parameters (i.e., Q=8, N=12, M=4).

The BICM encoder 2600 shown in FIG. 26 includes a main memory 2601, anLDPC controller 2611, a rotator 2612, a check node processor group 2613,a de-rotator 2614, a QB counter 2631, table A 2632, interleaver B 2633,a register group 2634, interleaver C 2635, and a mapper group 2651.

In FIG. 26, given that Q=8, the main memory 2601 reads eight bits at atime, the check node processor group 2613 includes eight check nodeprocessors, and the mapper group 2651 includes eight mappers. Also,given that M=4, the register group 2634 includes four registers.

The main memory 2601 receives a sequence of bits for transmission from,for example, the (non-diagrammed) input processor, and stores thereceived bit sequence.

The LDPC controller 2611 outputs a read address to the main memory 2601.The main memory 2601 accordingly outputs the bit sequence, eight bits ata time beginning with the lead bit, to the rotator 2612. The rotator2612 is controlled by the LDPC controller 2611 to perform apredetermined number of cyclical shifts on the eight bits suppliedthereto by the main memory 2601, and then outputs the eightcyclically-shifted bits to the check node processors of the check nodeprocessor group 2613, one bit at a time, the bits and the check nodeprocessors being in one-to-one correspondence. Each check node processorof the check node processor group 2613 is controlled by the LDPCcontroller 2611 to perform check node processing on each bit inputthereto, then outputs the results to the de-rotator 2614. The de-rotator2614 is controlled by the LDPC controller 2611 to perform apredetermined number of cyclic shifts on the eight bits received fromthe check node processor group 2613 so as to cancel the cyclic shiftapplied by the rotator 2612, and then outputs the eight shifted bits tothe main memory 2601. The LDPC controller 2611 outputs a write addressto the main memory 2601. The main memory 2601 accordingly stores theeight bits supplied thereto by the de-rotator 2614. The LDPC controller2611, the rotator 2612, the check node processor group 2613, and thede-rotator 2614 make up the BICM encoder in the LDPC encoder 2510 shownin FIG. 25.

The QB counter 2631 counts from 0 to 11 and outputs the counter value totable A 2632. The count operation of the QB counter 2631 is defined inconsideration of N=12.

Table A 2632 is a simple look-up table in which the cyclic blockpermutation rules are stored. That is, table A 2632 stores N=12 piecesof cyclic block read order information (information associating adifferent cyclic block with each of the 12 counter values from the QBcounter 2631). Table A 2632 outputs a read address to the main memory2601 such that the bits of one cyclic block (i.e., Q=8 bits)corresponding to the counter value supplied by the QB counter 2631 aresupplied from the main memory 2601 to interleaver B 2633. Thus, the mainmemory 2601 outputs the bits of one cyclic block corresponding to thecounter value of the QB counter 2631 to interleaver B 2633. Theprocessing using table A 2632 is executed as the cyclic blockpermutation process (stage A).

Interleaver B 2633 performs a predetermined number of cyclical shifts onthe bits of the cyclic block supplied by the main memory 2601, andoutputs the results to a first tier register of the register group 2634.The processing by interleaver B 2633 is executed as theintra-cyclic-block permutation process (stage B). Each register in theregister group 2634 stores one cyclic block of bits with timing matchingthe reception of a control pulse, and outputs the cyclic block of bitsbefore receiving the next control pulse.

When the QB counter 2631 performs the aforementioned process for countervalues 0 through 3, the bits of four cyclic blocks (i.e., 32 bits) areinput to interleaver C 2635. At this time, interleaver C 2635interleaves the bits of the four cyclic blocks input thereto, and themappers of the mapper group 2651 output one constellation word of bits(i.e., M=4 bits). Through the interleaving process, four bits, i.e., onefrom each of the four registers in the register group 2634, are suppliedto each mapper. This processing by interleaver C 2635 is executed as thecolumn-row permutation process (stage C).

The QB counter 2631, table A 2632, interleaver B 2633, the registergroup 2634, and interleaver C 2635 make up the bit interleaver 2520 ofthe BICM encoder shown in FIG. 25.

The mappers of the mapper group 2651 each map four bits supplied theretofrom interleaver C 2635 to a constellation, then output the results. Themapper group 2651 makes up the constellation mapper 2530 of the BICMencoder shown in FIG. 25.

For each codeword, the above-described set of processes is applied threetimes, once each for counter values 0-3, 4-7, and 8-11 of the QB counter2631.

The Embodiment depicted in FIG. 26 includes Q mappers operating inparallel. However, the mappers are also realizable as a BICM encoder soas to decrease or increase the parallelism. For example, the number ofparallel interleaver sections in the bit interleaver, i.e., the quotientof N/M, obviously may be increased so as to easily enhance parallelism.Such methods enable the parallelism to be optimized by parallelizing theQ×N/M mappers. Implementing such parallelism, without drawbacks, in thebit interleaver is beneficial.

The following describes a receiver receiving signals from a transmitterthat includes the bit interleaver performing a bit interleaving processthat satisfies Conditions 1 and 2, with reference to FIG. 27.

FIG. 27 is a block diagram of an example receiver, including anon-iterative BICM decoder, pertaining to a further Embodiment of thedisclosure. The receiver performs the transmitter operations in reverse.

The receiver 2700 shown in FIG. 27 includes a demodulator 2710 and anon-iterative BICM decoder (which in turn includes a constellationdemapper 2720, a bit deinterleaver 2730, and an LDPC decoder 2740).

The demodulator 2710 performs a demodulation process through OFDM, forexample, and outputs the demodulated results.

The constellation demapper 2720 of the non-iterative BICM decodergenerates a soft bit sequence by applying a demapping process to theinput from the demodulator 2710, and outputs the soft bit sequence sogenerated to the constellation demapper 2730. The soft bits are ameasure of probability that a given bit is a zero-bit or a one-bit.Typically, the soft bits are represented as log-likelihood ratios(hereinafter, LLRs), defined as follows.LLR(b)=ln[p(b=0)/p(b=1)]

where p(b=0) indicates the probability of the given bit b being azero-bit, and p(b=1) represents the probability of the given bit b beinga one-bit. Of course, p(b=0)+p(b=1)=1.

The bit deinterleaver 2730 performs an interleaving process (i.e., a bitde-interleaving process) on the soft bit sequence output from theconstellation demapper 2720 so as to cancel the bit interleaving processapplied to the bit sequence by the bit interleaver 2730 in thetransmitter illustrated in FIG. 25.

The LDPC decoder 2740 receives the soft bit sequence deinterleaved bythe bit deinterleaver 2730, and performs an LDPC decoding process usingthe soft bit sequence so received.

One improved technique offering significant performance gains isiterative BICM decoding. FIG. 28 illustrates an iterative BICM decoder.

FIG. 28 is a block diagram of an example receiver, including aniterative BICM decoder, pertaining to a further Embodiment of thedisclosure. The receiver performs the transmitter operations in reverse.

As shown in FIG. 28, a receiver 2800 includes the demodulator 2710 andan iterative BICM decoder (which in turn includes the constellationdemapper 2720, the bit deinterleaver 2730, the LDPC decoder 2740, asubtractor 2760, and a bit interleaver 2750).

The receiver 2800 of FIG. 28 has the constellation demapper 2720performing a constellation demapping process, the bit deinterleaver 2730performing a bit deinterleaving process, and the LDPC decoder 2740performing an LDPC decoding process.

After one or more LDPC decoding iterations, extrinsic information,obtained by the subtractor 2760 subtracting the input to the LDPCdecoder 2740 from the output of the LDPC decoder 2740, is output to thebit interleaver 2750. The bit interleaver 2750 performs an interleavingprocess on the extrinsic information using the same interleaving rulesas those applied to the bit sequence by the bit interleaver of thetransmitter depicted in FIG. 25. The bit interleaver 2750 then feedsback the interleaved extrinsic information to the constellation demapper2720. The constellation demapper 2720 uses the extrinsic information sofed back as a-priori information to compute more reliable LLR values.The bit deinterleaver 2730 then performs an interleaving process on thenewly computed LLR values (i.e., a bit de-interleaving process) so as tocancel the bit interleaving process applied to the bit sequence by thebit interleaver in the transmitter depicted in FIG. 25 and restore theoriginal order of the bit sequence. The LDPC decoder 2740 uses the LLRvalues so de-interleaved in the LDPC decoding process.

As shown in FIG. 28, an iterative decoding loop is made up of fourelements, namely the constellation demapper 2720, the bit deinterleaver2730, the LDPC decoder 2740, and the bit interleaver 2750. The bitdeinterleaver 2730 and the bit interleaver 2750 have beneficially verylow latency, ideally zero, and low complexity. This results in a moreefficient receiver implementation. The bit deinterleaver 2730 and thebit interleaver 2750 described above satisfy both of these conditions.

FIG. 29 illustrates an iterative BICM decoder realizing very efficientparallel implementation.

FIG. 29 is a block diagram of an example BICM decoder pertaining to afurther Embodiment of the disclosure. In FIG. 29, the BICM decoder 2900corresponds to the above-given parameters (i.e., Q=8, N=12, M=4).

As shown, the BICM decoder 2900 includes a main LLR memory 2901, abuffer LLR memory 2902, an LDPC controller 2911, a rotator 2912, a checknode processor group 2913, a de-rotator 2914, a QB counter 2931, table A2932, a subtractor group 2933, interleaver B 2934, register group 2935,interleaver C 2936, a demapper group 2937, deinterleaver C 2938,register group 2939, deinterleaver B 2940, and a delayer 2941.

In FIG. 29, given that Q=8, the main LLR memory 2901 and the buffer LLRmemory 2902 each read eight LLR values at a time, the check nodeprocessor group 2913 includes eight check node processors, and thedemapper group 2951 includes eight demappers. Also, given that M=4, theregister groups 2935 and 2972 each include four registers.

The demappers in the demapper group 2937 each perform a demappingprocess on the output of a demodulator (not diagrammed), then outputsthe LLR values so obtained to deinterleaver C 2938. The demapper group2937 makes up the constellation demapper 2720 of the iterative BICMdecoder shown in FIG. 28.

Deinterleaver C 2938 applies a deinterleaving process to the LLR values(i.e., a new interleaving process cancelling the interleaving processapplied by the transmitter during stage C), then outputs thedeinterleaved LLR values to the registers of the register group 2939.Each register stores one cyclic block of LLR values (i.e., eight LLRvalues). In register group 2939, the cyclic block of LLR values storedby each register is sequentially output to a later tier such that thecontent of each register is sequentially updated. Deinterleaver B 2940applies a deinterleaving process to the cyclic block of (eight) LLRvalues (i.e., a new interleaving process cancelling the interleavingprocess applied by the transmitter during stage B), then writes theresults to the main LLR memory 2901 and the buffer LLR memory 2902 inaccordance with table A 2932 (discussed later). An interleaving processcancelling the interleaving process applied by the transmitter duringstage A is achieved by this writing to the main LLR memory 2901 and thebuffer LLR memory 2902 in accordance with the content of Table A 2932.

Thus, the main LLR memory 2901 stores the post-deinterleaving LLRvalues, and is also used by the LDPC decoder (i.e., the LDPC controller2911, the rotator 2912, the check node processor group 2913, and thede-rotator 2914). The LDPC decoding process is an iterative processinvolving one or more iterations. In each LDPC decoding iteration, theLLR values in the main LLR memory 2901 are updated. In order to computethe extrinsic information needed for iterative BICM decoding, the oldLLR values are saved in the buffer LLR memory 2902.

The following describes the LDPC decoder operations.

The LDPC controller 2911 outputs the read address to the main LLR memory2901 in accordance with the parity-check matrix of the LDPC codes. Thus,the main LLR memory 2901 sequentially outputs one cyclic block of LLRvalues to the rotator 2912. The rotator 2912 is controlled by the LDPCcontroller 2911 to perform a predetermined number of cyclical shifts onthe cyclic block of LLR values supplied sequentially by the main LLRmemory 2901, then outputs the LLR values so shifted to the check nodeprocessors of the check node processor group 2913 one at a time. Thecheck node processors of the check node processor group 2913 arecontrolled by the LDPC controller 2911 to perform a check node processon the sequence of LLR values sequentially input thereto. Next, thecheck node processors of the check node processor group 2913 arecontrolled by the LDPC controller 2911 to sequentially output the LLRvalues resulting from the check node process. The de-rotator 2914 iscontrolled by the LDPC controller 2911 to performs a predeterminednumber of cyclic shifts cancelling the cyclic shift applied to thecyclic block sequentially received from the check node processor group2913 by the rotator 2912, then sequentially outputs the shifted resultsto the main LLR memory 2901. The LDPC controller 2911 outputs the writeaddress to the main LLR memory 2901 in accordance with the parity-checkmatrix of the LDPC codes. Thus, the main LLR memory 2901 stores thecyclic block of results sequentially supplied thereto by the de-rotator2914. The LDPC controller 2911 repeatedly executes the above-describedprocessing in accordance with the parity-check matrix of the LDPC codes.

After a predetermined number of LDPC iterations, a BICM iteration isperformed. The LDPC and BICM iterations are also respectively referredto as inner and outer iterations. These two types of iterative may alsooverlap in some implementations. This enables the speed of convergenceto be increased. The BICM and LDPC decoding processes are well known inthe field, and the details thereof are thus omitted.

The QB counter 2931 counts from 0 to 11 and outputs the counter value totable A 2932. The count operation of the QB counter 2931 is defined inconsideration of N=12.

Table A 2932 is a simple look-up table in which the cyclic blockpermutation rules are stored. That is, table A 2932 stores N=12 piecesof cyclic block read (and write) order information (i.e., withinformation associating a different cyclic block with each of the 12counter values from the QB counter 2631). Table A 2932 outputs the readaddress to the main LLR memory 2901 and to the buffer LLR memory 2902such that one cyclic block of LLR values corresponding to the countervalue supplied by the QB counter 2931 are supplied to the subtractorgroup 2933 by the main LLR memory 2901 and to the buffer LLR memory2902. Thus, the main LLR memory 2901 and the buffer LLR memory 2902 eachoutput a cyclic block of LLR values corresponding to the counter valueof the QB counter 2931 to the subtractor 2933. The delayer 2941 makes adelay adjustment such that the position of the LLR value read from themain LLR memory 2901 and the buffer LLR memory 2902 match the writeposition of the same LLR values to the main LLR memory 2901 and thebuffer LLR memory 2902. The processing using table A 2932 is executed asthe cyclic block permutation process (stage A).

The subtractor 2933 in the subtractor group subtracts the output of thebuffer LLR memory 2902 from the output of the main LLR memory 2901, thenoutputs the extrinsic information for one cyclic block thus obtained(i.e., eight pieces of extrinsic information) to interleaver B 2934.

Interleaver B 2634 performs a predetermined number of cyclical shifts onthe pieces of extrinsic information for one of the cyclic blockssupplied by the subtractor 2933, and outputs the results to a first tierregister of the register group 2935. The processing performed byinterleaver B 2934 corresponds to the intra-cyclic-block permutation(stage B). Each register in the register group 2935 stores eight bitswith timing matching the reception of a control pulse, and outputs theeight bits before receiving the next control pulse.

When the QB counter 2631 performs the aforementioned process for countervalues 0 through 3, the extrinsic information for four cyclic blocks(i.e., 32 pieces of extrinsic information) are input to interleaver C2936. At this time, interleaver C 2936 performs an interleaving processon the extrinsic information input thereto for four cyclic blocks, thenoutputs one constellation word of extrinsic information (i.e., M=4pieces of extrinsic information) to each demapper of the demapper group2937. Through the interleaving process, the four pieces of extrinsicinformation are supplied to the demappers of the demapper group 2951from the four registers in register group 2935, one at a time. Thisprocessing by interleaver C 2936 is executed as the column-rowpermutation process (stage C).

The QB counter 2931, table A 2932, interleaver B 2934, the registergroup 2935, and interleaver C 2936 make up the bit interleaver 2750 ofthe BICM decoder shown in FIG. 28.

The demappers of the demapper group 2937 uses the four pieces ofextrinsic information supplied by interleaver C 2936 as a-prioriinformation to perform a demapping process, then output the resultingLLR values to deinterleaver C 2938.

Deinterleaver C 2938 applies a deinterleaving process to the LLR values(i.e., a new interleaving process cancelling the interleaving processapplied by the transmitter during stage C), then outputs thedeinterleaved LLR values to the registers of the register group 2939.Each register stores one cyclic block of LLR values (i.e., eight LLRvalues). In register group 2939, the cyclic block of LLR values storedby each register is sequentially output to a later tier such that thecontent of each register is sequentially updated. Deinterleaver B 2940applies a deinterleaving process to the cyclic block of (eight) LLRvalues (i.e., a new interleaving process cancelling the interleavingprocess applied by the transmitter during stage B), then writes theresults to the main LLR memory 2901 and the buffer LLR memory 2902. Themain LLR memory 2901 and the buffer LLR memory 2902 receive the writeaddress from table A 2932 via the delayer 2941, then store one cyclicblock of LLR values (i.e., eight LLR values) received from thedeinterleaver 2940 in accordance with the received write address. Aninterleaving process cancelling the interleaving process applied by thetransmitter during stage A (i.e., a deinterleaving process) is achievedby this writing in accordance with the content of table A 2932.

For each codeword, the above-described set of processes is applied threetimes, once each for counter values 0-3, 4-7, and 8-11 of the QB counter2931.

The QB counter 2931, table A 2932, deinterleaver B 26938, the registergroup 2939, and interleaver C 2940 make up the bit interleaver 2730 ofthe BICM decoder shown in FIG. 28.

Interleaver B 2934 and deinterleaver B 2940 are reconfigurable. Thisrequires a certain hardware cost, but this cost is minimized byattentive design. Interleaver C 2936 and deinterleaver 2938 implementthe column-row permutation. This permutation is uniform for apredetermined constellation size. Thus, the cost of implementation isreduced.

The Embodiment depicted in FIG. 29 includes Q demappers operating inparallel. However, the demappers are also realizable as an iterativeBICM decoder by decreasing or increasing the parallelism. For example,the number of parallel interleaver sections in the bit interleaver,i.e., the quotient of N/M, obviously may be increased so as to easilyenhance parallelism. Such methods enable the parallelism to be optimizedby parallelizing the Q×N/M demappers. The above-described bitinterleaver has the merit of being Implementable with Such Parallelismwithout Trouble.

(Further Experimenter Discoveries)

The interleavers satisfying Conditions 1 and 2 given above (i.e.,parallel interleavers) assume that the number of bits per constellationword M is a divisor of the number of cyclic blocks N. However, M is nottypically a divisor of N. For example, the 16K LDPC codes used in theDVB-T2 standard has N=45 cyclic blocks per 16K LDPC codeword. When M isnot a divisor of N, the mapping of square constellations, such as QAMconstellations where M is even, is not straightforward.

Thus, a particular solution is proposed that involves excluding one ormore of the N cyclic blocks and implementing the interleaver discussedin Embodiment 1 (i.e. the parallel interleaver), above, only to theremaining cyclic blocks.

In other words, N′ cyclic blocks are selected from among the N cyclicblocks such that N′ is a multiple of the number of bits perconstellation words Min the bit interleaver. The bit interleaver dividesthe N′ selected cyclic blocks into N′/M sections such that each sectionincludes M cyclic blocks, then performs a section permutation on eachsection. The bits of the excluded (i.e., not selected) cyclic block mayor may not be interleaved.

For example, the excluded cyclic blocks may be the cyclic blocks havinga variable node of the lowest weight. For the example RA QC LDPC codes(see FIG. 5), the excluded cyclic blocks are the cyclic block of theparity section (having a variable node weight of two), and arebeneficially the last one or more cyclic blocks of the codeword.

FIG. 30 illustrates a cyclic block subject to and a cyclic blockexcluded from (i.e., an excluded block of) the interleaving processdescribed above (i.e., Embodiment 1). In FIG. 30, the code is 16K LDPCcode conforming to the DVB-T2 standard, and the constellation is a16-QAM constellation. As shown, 44 of the cyclic blocks are subject tointerleaving (i.e., blocks 1 through 44), and cyclic block 45, in thelast row, is the one cyclic block not subject to interleaving (i.e., theexcluded block). The four blackened squares represent the four bits ofthe first constellation.

In general, the number of interleaver sections (each made up of M cyclicblocks) is given by floor(N/M), and the number of excluded cyclic blocksis given by rem(N, M). Here, floor(N/M) is a function that returns thelargest integer smaller than or equal to N/M, and rem(N, M) is afunction that returns the remainder of dividing N by M.

Table 2 indicates the number of sections and the number of excludedcyclic blocks for various constellation sizes (i.e., number of bits perconstellation M), for the 16K LDPC codes of the DVB-T2 standard (whereN=45 cyclic blocks are used).

TABLE 2 Constellation size M No. of sections No. of excluded blocks QPSK2 22 1 16-QAM 4 11 1 64-QAM 6 7 3 256-QAM  8 5 5

According to the interleaving method satisfying Conditions 1 and 2 asdescribed above, each constellation word is mapped onto M cyclic blocks.However, for large constellations (i.e., constellations having manyconstellation points), an interleaving method satisfying Conditions 1and 2 requires an extremely large amount of delay registers (see theimplementation described with reference to FIGS. 26 through 29). Usingan extremely large amount of registers leads to an increase in circuitarea and electric power consumption. In addition, reducing the number ofcyclic blocks onto which each constellation word is mapped is beneficialfor increasing the overlap between the outer (BICM) iterations and theinner (LDPC) iterations, in turn reducing overall BICM decoding latency.

By mapping two or more bits of each constellation word onto the samecyclic block, the number of cyclic blocks onto which each constellationword is mapped is reduced. The number of constellation word bits mappedonto the same cyclic block is termed the folding factor and is denotedF. For example, when F=2 for a 16-QAM constellation, each constellationword is mapped onto four cyclic blocks rather than two. The onlyconstraint is that the folding factor F (which is an integer greaterthan one) must be a divisor of both M and Q. When F=1, no folding isinvolved, i.e., the situation corresponds to Embodiment 1, describedabove.

A complex QAM constellation symbol is decomposed into two identical realPAM symbols. Thus, the M bits of the QAM constellation are divided intotwo identical real PAM symbols, which are sets of M/2 bits. The bits ofeach constellation word are then mapped onto the same number M/2 ofcyclic blocks. A folding factor of F=2 is advantageous for QAMconstellation.

For complex constellations that cannot be decomposed into real numbers,such as 8-PSK (phase shift keying), 16-APSK (amplitude phase shiftkeying), 32-APSK and so on in the DVB-S2 standard, the folding method isnot easily applicable. However, the folding method is usable when F is adivisor of M. Unfortunately, this prevents any guarantee that eachcyclic block has only bits of the same robustness level from theconstellations mapped thereto.

Beneficially, the folding method is, for example, applied such that onlybits of the same robustness level in the constellations are mapped tothe cyclic blocks.

Folding is also beneficial in reducing the number of excluded cyclicblocks, or even eliminating the need to exclude any cyclic blocks. Asdescribed above, a certain number of cyclic blocks making up thecodeword must be excluded when the interleaver described in Embodiment 1(i.e., a parallel interleaver) is used.

Without folding (i.e., when F=1), the number of groups of M cyclicblocks (i.e., the number of sections) is floor(N/M), and the number ofexcluded cyclic blocks is rem(N, M). With folding, the number of groupsof M/F cyclic blocks is floor(N/(M/F)), and the number of excludedcyclic blocks is rem(N, M/F). Specific example of these numbers aregiven in Table 3, for the LDPC codes used in the DVB-T2 standard.

TABLE 3 Without folding With folding LDPC Constel- No. of No. ofcodeword lation No. of excluded No. of excluded length size M sectionsblocks sections blocks 16K QPSK 2 22 1 44 1 (N = 45, 16-QAM 4 11 1 22 1Q = 360) 64-QAM 6 7 3 15 0 256-QAM 8 5 5 11 1 64K QPSK 2 90 0 180 0 (N =180, 16-QAM 4 45 0 90 0 Q = 360) 64-QAM 6 30 0 60 0 256-QAM 8 22 4 45 0

The inventor discovered that, in order to perform folding (where F is aninteger equal to or greater than two), Conditions 1 and 2 must bemodified into Conditions 1A and 2A, as given below.

(Condition 1A)

The M bits of each constellation word are each mapped to one of M/Fdifferent cyclic blocks of the LDPC codeword. This is equivalent tomapping one bit from M/F different cyclic blocks of the LDPC codeword toa constellation word. This is schematically illustrated in FIG. 31A.

(Condition 2A)

All constellation words mapped to the M/F cyclic blocks are mapped onlyto that particular cyclic block. This is equivalent to mapping all M×Q/Fbits of the M/F different cyclic blocks each made up of Q bits toexactly Q/F constellations. This is schematically illustrated in FIG.31B.

When F=1, no folding is involved, and thus Conditions 1A and 2A areequivalent to Conditions 1 and 2.

Embodiment 2

The following describes the details of a bit interleaver (i.e., aparallel bit interleaver) that satisfies conditions 1A and 2A, givenabove. In the following description, processing and the units performingsuch processing are labeled with the same reference numbers whereverapplicable.

In the present document, each group of M/F cyclic blocks or of Q/Fconstellation words is referred to as a folding section (or as a foldinginterleaver section).

When F=1 (i.e., no folding), the folding interleaver sections match theinterleaver sections and the bit interleaver is configured identicallyto the bit interleaver from Embodiment 1.

Folding occurs when F is an integer greater than one. Embodiment 2describes an example of folding where F=2.

FIG. 32 is a block diagram illustrating the configuration of a bitinterleaver satisfying Conditions 1A and 2A, when Q=8, M=4, N=12, andF=2, as another Embodiment of the disclosure.

In FIG. 32, the QC-LDPC codewords are made up of N=12 cyclic blocks QB1through QB12, each in turn made up of Q=8 bits. Each of the 24constellation words is made up of M=4 bits. Each constellation wordindicates one of 2^(M)=16 constellation points. The bit interleaver isdivided into F×N/M=6 folding sections, and 24 constellation words areeach associated with one of the F×N/M=6 folding sections.

The bit interleaver 2000A includes a bit permutator 2010A. The bitpermutator 2010A includes F×N/M=6 folding section permutators2021A-2026A each operating independently. Rather than providing sixfolding section permutators, a single folding section permutator may beprovided so as to performs six (later described) folding sectionpermutation processes, switching therebetween over time.

The folding section permutators (2021A, 2022A, 2023A, 2024A, 2025A,2026A) are independent and each apply a folding section permutationprocess to the 16 bits of two cyclic blocks such that F=2 bits from eachof M/F=2 cyclic blocks (QB1-QB2, QB3-QB4, QB5-QB6, QB7-QB8, QB9-QB10,QB11-QB12) are mapped to a given set of four constellation words (C1-C4,C5-C8, C9-C12, C13-C16, C17-C20, C21-C24).

Conditions 1A and 2A, described above, simply ensure that the bitinterleaver is divisible into F×N/M parallel folding sections. Thefolding section permutations applied to the parallel folding sectionsmay all apply the same permutation rules, may each apply differentpermutation rules, or may involve a subset of the sections applyingidentical permutation rules while other differ.

For example, the folding section permutators may map Q bits from eachcyclic block to bits of Q/F constellation words having the samerobustness level. This is illustrated in FIGS. 33A, 33B, 34A, and 34Bfor a situation where Q=8 and M=4.

FIG. 34A is a block diagram of a (folding) section permutator when F=1(i.e., without folding), and is similar to FIG. 22A.

FIG. 34B is a block diagram of two folding section permutators from FIG.32 where F=2 (i.e., with folding).

However, in the example of FIG. 34B, the constellations are 16-QAMconstellations. Thus, the bits of the constellations have two robustnesslevels. Bits b1 and b3 have the same robustness level, and bits b2 andb4 have the same robustness level, the former robustness level beingdifferent from the latter robustness level.

The folding section permutators 2201A (and 2202A) each include acolumn-row permutator 2131A (or 2132A).

The column-row permutators 2131A (and 2132A) each perform a column-rowpermutation process on Q×M/F=16 cyclic blocks QB1 and QB2 (or QB3 andQB4). To be exact, the column-row permutators 2131A (and 2132A) writeQ×M/F=16 bits row-wise into a Q×M/F (8×2) matrix, then read the 16 bitsso written column-wise to perform the column-row permutation process.The column-row permutation applied by the column-row permutators 2131Aand 2132A resembles the permutation applied to the 12×1350 matrix shownin FIGS. 9A and 9B, where Q columns and M/F rows are used, the writingprocess occurs row-wise, and the reading process occurs column-wise.

Folding with a folding factor of F reduces the number of cyclic blocksmapped to a single constellation word. Thus, the matrix used in thecolumn-row permutation is reduced in size, from M rows to M/F rows.

FIG. 33A illustrates the mapping function performed by the (folding)section permutator from FIG. 34A. FIG. 33B illustrates the mappingfunction performed by the two folding section permutators from FIG. 34B.In FIGS. 33A and 33B, each constellation word of M=4 bits is denoted b1through b4. The portions outlined in thicker lines represent theportions mapped to constellation C1.

As shown in FIGS. 33A and 34A, the eight bits of a cyclic block (beingof equal importance) are each mapped to the bits of eight constellationwords having the same bit index (i.e., having the same robustnesslevel). Also, in FIGS. 33B and 34B, the eight bits of a cyclic block(being of equal importance) are mapped to the bits of four constellationwords having the same robustness level.

The folding section permutation described in FIG. 34B may be applied tocyclic blocks QB5-QB6, QB7-QB8, QB9-QB10, and QB11-QB12.

The folding section permutators of FIGS. 34A and 34B may also include asubunit performing an intra-cyclic-block permutation on the bits ofcyclic blocks QB1-QB4 prior to the column-row permutation.

Advantageously, an additional cyclic block permutation may be applied tothe N cyclic blocks before the bit interleaver performs the foldingsection permutation. FIG. 35 is a structural diagram of the additionalcyclic block permutation applied by the bit interleaver.

The bit interleaver 2300A shown in FIG. 35 includes the cyclic blockpermutator 2310 and a bit permutator 2010A (which in turn includesfolding section permutators 2021A-2026A).

FIG. 36 is a schematic block diagram of the bit interleaver 3500 shownin FIG. 23.

The bit interleaver 2400A shown in FIG. 36 includes the cyclic blockpermutator 2310 and a bit permutator 2200A (which in turn includesfolding section permutators 2201A-2206A).

The folding section permutators 2201A-2206A each include a column-rowpermutator 2131A-2136A. The folding section permutators 2133A-2136A eachperform substantially identical permutations with the column-rowpermutators 2131A-2132A.

The bit interleavers shown in FIGS. 35 and 36 may each include anadditional subunit performing an intra-cyclic-block permutation on thebits of cyclic blocks QB1-QB12 before or after the cyclic blockpermutation.

The following describes a transmitter that includes the bit interleaverperforming a bit interleaving process that satisfies Conditions 1A and2A, with reference to FIG. 37.

FIG. 37 is a block diagram of a transmitter pertaining to a furtherEmbodiment of the present disclosure. The transmitter 2500A shown inFIG. 37 is configured similarly to the transmitter 2500 of FIG. 25,differing in that the bit interleaver 2520 is replaced with a bitinterleaver 2520A.

The bit interleaver 2520A receives the codeword in QC-LDPC code from theLDPC encoder 2510. The codeword is made up of N=12 cyclic blocks, eachcyclic block including Q=8 bits. The bit interleaver 2520A performsinterleaving on the bits of the codewords. The bit interleaver 2520Adivides the interleaved codeword into a plurality of constellationwords, each made up of M=4 bits and indicating one of 2^(M)=16constellation points, then outputs the constellation words to theconstellation mapper 2530. The bit interleaver 2520A may apply the bitinterleaving process discussed with reference to FIGS. 32 through 34, ormay apply a variant bit permutation process (excluding cases where F=1).Also, the bit interleaver 2520A may apply an additional cyclic blockpermutation process (excluding cases where F=1), such as the processdiscussed with reference to FIGS. 35 and 36 or a variation thereof.

The following describes a receiver receiving signals from a transmitterthat includes the bit interleaver performing a bit interleaving processthat satisfies Conditions 1A and 2A.

FIG. 38 is a block diagram of an example receiver, including anon-iterative BICM decoder, pertaining to a further Embodiment of thedisclosure. The receiver performs the transmitter operations in reverse.The receiver 2700A shown in FIG. 38 is configured similarly to thereceiver 2700 of FIG. 27, differing in that the bit deinterleaver 2730is replaced by a bit deinterleaver 2730A.

The bit deinterleaver 2730A performs an interleaving process on the softbit sequence output from the constellation demapper 2720 so as to cancelthe bit interleaving process applied to the bit sequence by the bitinterleaver 2520A in the transmitter 2500A.

FIG. 39 is a block diagram of an example receiver, including anon-iterative BICM decoder, pertaining to a further Embodiment of thedisclosure. The receiver performs the transmitter operations in reverse.The receiver 2800A shown in FIG. 39 is configured similarly to thereceiver 2800 of FIG. 28, differing in that the bit deinterleaver 2730and the bit interleaver 2750 are replaced by a bit deinterleaver 2730Aand a bit deinterleaver 2750A.

The bit interleaver 2750A performs an interleaving process on theextrinsic information using the same interleaving rules as theinterleaving process applied to the bit sequence by the bit interleaver2520A in the transmitter 2500A.

From a hardware implementation perspective, folding is desirable inthat, for example, the bits of a constellation are thereby located infewer LLR memory locations. Typically, the LLR memory in the decoderincludes G×N addressable memory locations, each location being capableof storing Q/G LLR values. Here, G is an implementation parameter thatis a divisor of Q and is hereinafter referred to as memory granularity.The LLR memory locations in the decoder and the LLR values of the firstconstellation are shown in FIG. 40, where M=4, F=2, Q=12, and G=1-12.

The number of LLR values per memory location, i.e., the value of Q/G, isnecessarily a multiple of F. The LLR values of each constellation arethus stored at the same position in all memory locations. This ensuresthat the LLR values of any constellation word are stored in M/F memorylocations. A counter-example is given in FIG. 40 where G=4, and 12/4=3LLR values are stores at each memory location. The LLR values of thesecond and fifth constellation words are each stored at four memorylocations rather than at two memory locations.

In addition to simple QAM constellations where folding with F=2 isapplicable, folding is even more useful when two or more constellationsymbols are jointly decoded. Joint decoding is necessary, for instance,for the maximum-likelihood decoding of block codes (e.g., space-timecodes, space-frequency codes, and the like), and for rotatedconstellations in two or more dimensions.

In genera_(l), a b_(l)oc_(k) code encodes two or more input symbo_(l)s(e.g., x₁, . . . , x_(K)) onto two or more output symbo_(l)s (e.g., y₁,. . . , y_(L)). Here, L is at least equal to K. The block codes aremodeled on an L×K generator matrix. Here, the output signal vector Y isobtained as a result of left-multiplying the input signal vector X bythe generator matrix G (i.e., Y=GX).

The elements of the input signal vector X and the output signal vectorY, as well as the elements of the generator matrix G, may be real orcomplex. Depending on the type of code, the output signal vector Y maybe transmitted in different time slots or in different frequency slots,may be transmitted over different antennas, or may be transmitted usinga variety of different time slots, frequency slots, and antennas.

In the receiver, maximum-likelihood decoding is required in order todecode all elements of the input signal vector X Examples of block codesfor multiple-input multiple-output (hereinafter, MIMO) systems includeAlamouti codes, Golden codes, and spatial multiplexing.

When K symbols are encoded in the same block, a folding factor of up toK is obviously useable. Further, provided that the symbols are QAMsymbols (including two divisible PAM symbols), then the folding factormay be increased to 2K.

According to a further aspect of the present disclosure, whenconstellations of different sizes, i.e., hybrid constellations, arejointly encoded, the two constellations have different robustnesslevels. Thus, for example, the cyclic block to which the bits of oneconstellation word are mapped is distinct from the cyclic block to whichthe bits of the other constellation word are mapped.

The following describes an example of a coded spatial-multiplexing MIMOsystem using two transmit antennas. The complex signal prior to codingis X=[x₁ x₂]. Here, x₁ is a signal to which QPSK has been applied, andx₂ is a signal to which 16-QAM has been applied. The complex signalafter decoding is Y=[y₁ y_(z)]. Here, y₁ and y₂ are signals respectivelytransmitted by a first antenna and a second antenna. Y is obtainedthrough a left-multiplication of X with a 2×2 generator matrix G (wherethe elements of G may be either real or complex) (i.e., Y=GX).

FIG. 41 illustrates an example of mapping with a folding factor of F=2,when multiplexing QPSK symbols with 16-QAM symbols in a single blockcode. FIG. 41 indicates only the first seven bits of the cyclic blocks.The two complex symbols x₁ and x₂ are configured as follows.

x1 is a QPSK symbol having a real part b1 and an imaginary part b2.

x2 is a 16-QAM symbol having real part b3 and b4 and having imaginaryparts b5 and b6.

The two symbols are jointly decoded by the receiver and thus form aconstellation block or generated block.

The entire 6-bit constellation block has three robustness levels.

Level 1: 1: QPSK bits b1 and b2 are mapped to QB1

Level 2: 16-QAM bits b3 and b5 are mapped to QB2

Level 3: 16-QAM bits b4 and b6 are mapped to QB3

When one of the constellations has M1 bits and the other constellationhas M2 bits, the N cyclic groups are divided into one or more groups ofM1 cyclic block and one or more groups of M2 cyclic blocks in order toperform the bit interleaving process.

Embodiment 3

The following describes an example of an interleaver performing foldingin a situation where N is not a multiple of M.

FIG. 42 illustrates a cyclic block subject to and a cyclic blockexcluded from (i.e., an excluded block) the interleaving process whereF=2, described above. In FIG. 42, the code is 16K LDPC code conformingto the DVB-T2 standard, and the constellation is a 16-QAM constellation.As shown, 44 of the cyclic blocks are subject to interleaving (i.e.,blocks 1 through 44), and cyclic block 45, in the last row, is the onecyclic block not subject to interleaving (i.e., the excluded block). Thefour blackened squares represent the four bits of the firstconstellation.

FIG. 43 is a schematic block diagram of a bit interleaver performingfolding when N is not a multiple of M. For simplicity, the followingvalues hold: N=13, Q=8, M=4, and F=2.

The number of folding sections is floor(N/(M/F))=6, and the number ofexcluded cyclic blocks is rem(N, M/F)=1.

The bit interleaver 2000B selects 13−1=12 cyclic blocks from amongcyclic blocks QB1-QB13, such that the selected cyclic blocks QB1-QB12satisfy conditions A1 and A2 and are subject to interleaving. The bitpermutator 2010A in the bit interleaver 2000B performs the permutationprocess described with reference to FIG. 32 on the twelve selectedcyclic blocks. Although the bits of cyclic block QB13 are here mapped toa constellation word without interleaving, interleaving may also beapplied prior to mapping to the constellation word.

As an example of an interleaver not performing folding when N is not amultiple of M, the bit permutator 2010A shown in FIG. 43 may be replacedby the permutator 2010 shown in FIG. 20.

(Supplement 1)

The present disclosure is not limited to the Embodiments describedabove. Provided that the aims of the invention and accompanying aims areachieved, other variations are also possible, such as the following.

(1) Embodiment 1 is described above using the parameters N=12, Q=8, andM=4. However, no limitation to the parameters N, M, and Q is intended.Here, N may be any multiple of M. When N is two or more times M, theprocessing by the bit interleaver is divisible into a plurality ofsections.(2) In Embodiment 2, when folding is used, i.e., when F is two orgreater, the parameters given for the example are N=12, Q=8, M=4, and afolding factor of F=2. However, no limitation to the parameters N, M, Q,and F is intended. Here, F is a divisor of M and Q, and N is a multipleof M/F.(3) In Embodiment 2, when folding is used, the value of F is given astwo, which is the number of bits having the same robustness level in asingle 16-QAM constellation. However, no limitation is intended. Thevalue of F need not be equal to the number of bits having the samerobustness level in a constellation, and may indeed be other than thenumber of bits having the same robustness level in a constellation.(4) In Embodiment 2, when folding is used, the example describes afolding factor of F=2, and QAM constellations being 16-QAMconstellations. However, no limitation is intended. When F=2, the QAMconstellations may be other than 16-QAM constellations (e.g., 64-QAMconstellations or 256-QAM constellations).(5) In the above-described Embodiments, the constellations are describedas 16-QAM (i.e., M=4). However, the constellations may be specified byother modulation methods such as QPSK and QAM, such as the circularconstellations employed in the DVB-S2 standard, higher-dimensionalconstellations, and so on.(6) The methods and devices discussed in the above Embodiments may beimplemented as software or as hardware. No particular limitation isintended in this regard. Specifically, the above-described Embodimentsmay be implemented as a computer-readable medium having embodied thereoncomputer-executable instructions that are adapted for allowing acomputer, a microprocessor, a microcontroller, and the like to executethe above-described methods. Also, the above-described Embodiments maybe implemented as an Application-Specific Integrated Circuit (ASIC) oras an Field Programmable Gate Array (FPGA).

(Supplement 2)

The bit interleaving method, bit interleaver, bit deinterleaving method,bit deinterleaver, and decoder of the present disclosure, and theeffects thereof, are described below.

In a first aspect of a bit interleaving method, a bit interleavingmethod for a communication system using quasi-cyclic low-density paritycheck codes comprises: a reception step of receiving a codeword of thequasi-cyclic low-density parity check codes made up of N cyclic blockseach including Q bits; a bit permutation step of applying a bitpermutation process to the codeword so as to permute the bits in thecodeword; and a division step of dividing the codeword, after the bitpermutation process, into a plurality of constellation words, each ofthe constellation words being made up of M bits and indicating one of2^(M) constellation points in a predetermined constellation, whereinprior to the bit permutation process, the codeword is divided into F×N/Mfolding sections, F being an integer greater than one, each of thefolding sections including M/F of the cyclic blocks, and each of theconstellation words being associated with one of the F×N/M foldingsections, and in the bit permutation step, the bit permutation processis applied such that the M bits in each of the constellation wordsinclude F bits from each of M/F different cyclic blocks in a givenfolding section associated with a given constellation word, and suchthat all bits in the given folding section are mapped to only Q/F of theconstellation words associated with the given folding section.

In another aspect, a first bit interleaver for a communication systemusing quasi-cyclic low-density parity check codes comprises: a bitpermutation unit receiving a codeword of the quasi-cyclic low-densityparity check codes made up of N cyclic blocks each including Q bits,applying a bit permutation process to the codeword so as to permute thebits in the codeword, and dividing the codeword, for output after thebit permutation process, into a plurality of constellation words, eachof the constellation words being made up of M bits and indicating one of2^(M) constellation points in a predetermined constellation, whereinprior to the bit permutation process, the codeword is divided into F×N/Mfolding sections, F being an integer greater than one, each of thefolding sections including M/F of the cyclic blocks, and each of theconstellation words being associated with one of the F×N/M foldingsections, and the bit permutation unit applies the bit permutationprocess such that the M bits in each of the constellation words includeF bits from each of M/F different cyclic blocks in a given foldingsection associated with a given constellation word, and such that allbits in the given folding section are mapped to only Q/F of theconstellation words associated with the given folding section.

Accordingly, reductions in circuit surface area and in electric powerconsumption are achieved, in addition to enabling the realization of abit interleaving process having high parallelism.

In a second aspect of the bit interleaving method, the bit permutationstep includes a folding section permutation step of independentlyapplying a folding section permutation process to each of the F×N/Mfolding sections so as to permute the bits in each of the foldingsections.

Also, in a second aspect of a bit interleaver, the bit permutation unitincludes a folding section permutation unit independently applying afolding section permutation process to each of the F×N/M foldingsections so as to permute the bits in each of the folding sections.

Accordingly, a plurality of folding section permutation processes areexecutable in parallel.

In a third aspect of the bit interleaving method, in the folding sectionpermutation step, the folding section permutation process is performedsuch that the Q bits in a given cyclic block are each mapped to a bit ofan identical robustness level in the Q/F constellation words associatedwith one of the folding sections that corresponds to the given cyclicblock.

Also, in a third aspect of a bit interleaver, the folding sectionpermutation unit applies the folding section permutation process suchthat the Q bits in a given cyclic block are each mapped to a bit of anidentical robustness level in the Q/F constellation words associatedwith one of the folding sections that corresponds to the given cyclicblock.

Accordingly, bits of the codeword having the same importance are mappedto bits of the constellation word having the same robustness level,allowing a matching of importance and robustness level. For example, thebit of the codeword having the highest importance may be mapped to a bitof the constellation word having the highest robustness level. In such acase, high reliability is achieved at reception time for the bit of thecodeword having the highest importance, resulting in greater receptioncapability.

In a fourth aspect of the bit interleaving method, F is equal to anumber of bits of an identical robustness level in one of theconstellation words.

Also, in a fourth aspect of a bit interleaver, F is equal to a number ofbits of an identical robustness level in one of the constellation words.

Accordingly, an effective hardware implementation is realized.

In a fifth aspect of the bit interleaving method, F=2, and theconstellation words are QAM constellations.

Also, in a fifth aspect of a bit interleaver, F=2, and the constellationwords are QAM constellations.

Accordingly, an effective hardware implementation is realized.

In a sixth aspect of the bit interleaving method, the folding sectionpermutation step includes a column-row permutation step of applying acolumn-row permutation process to the M/F×Q bits in each of the foldingsections so as permute the M/F×Q bits.

In a seventh aspect of the bit interleaving method, the column-rowpermutation process is equivalent to writing the M/F×Q bits row-wiseinto a matrix having Q columns and M/F rows, then reading the M/F×Q bitscolumn-wise.

Also, in a sixth aspect of a bit interleaver, the folding sectionpermutation unit applies a column-row permutation process to the M/F×Qbits in each of the folding sections so as permute the M/F×Q bits.

Accordingly, a column-row permutation is used in the folding sectionpermutation process, thus enabling the realization of an extremelyefficient folding section permutation process.

In a further aspect, a bit deinterleaving method for deinterleaving abit stream in a communication system using quasi-cyclic low-densityparity check codes comprises: a reception step of receiving a bitsequence made up of N×Q bits; and a reverse bit permutation step ofapplying a reverse bit permutation process to the received bit sequenceso as to permute the bits in the bit sequence in order to restore thecodeword of the quasi-cyclic low-density parity check codes, wherein thereverse bit permutation process reverses the bit permutation process inthe bit interleaving method of the first aspect.

In an alternate aspect, a bit deinterleaver for deinterleaving a bitstream in a communication system using quasi-cyclic low-density paritycheck codes comprises: a reverse bit permutation unit receiving a bitsequence made up of N×Q bits, and applying a reverse bit permutationprocess to the received bit sequence so as to permute the bits in thebit sequence in order to restore a codeword of the quasi-cycliclow-density parity check codes, wherein the reverse bit permutationprocess reverses the bit permutation process applied by the bitinterleaver of the first aspect.

In another aspect, a decoder for a bit interleaving and demodulatingsystem using quasi-cyclic low-density parity check codes, comprising: aconstellation demapper generating a soft bit sequence indicating aprobability of a corresponding bit being one of a zero-bit and aone-bit; the bit deinterleaver of the alternate aspect deinterleavingthe soft bit sequence; and a low-density parity check decoder decodingthe deinterleaved soft bit sequence.

In yet another aspect, the decoder of the other aspect furthercomprises: a subtraction unit subtracting input to the low-densityparity check decoder from output of the low-density parity checkdecoder; and the bit interleaver of the first aspect, providing thedifference from the subtraction unit to the constellation demapper asfeedback.

Accordingly, a bit interleaving process having high parallelism isrealizable.

INDUSTRIAL APPLICABILITY

The present invention is applicable to a bit interleaver in abit-interleaved coding and modulation system used for quasi-cycliclow-density parity codes, and to a bit deinterleaver corresponding tosuch a bit interleaver.

REFERENCE SIGNS LIST

-   2000A Bit interleaver-   2010A Bit permutator-   2021A Folding section permutator-   2131A, 2132A Column-row permutator-   2500A Transmitter-   2510 LDPC encoder-   2520A Bit interleaver-   2530 Constellation mapper-   2700A, 2800A Receiver-   2710 Constellation demapper-   2720A Bit deinterleaver-   2730 LDPC decoder-   2740 Subtractor-   2750A Bit interleaver

The invention claimed is:
 1. A transmitting method performed by a bitinterleaver for transmitting a transmission signal generated from bitsof a codeword, the codeword being generated by using a repeat-accumulatequasi-cyclic low-density parity check coding scheme, the bit interleaverincluding a non-transitory memory storing information indicating apermutation rule and circuitry that reorders parity portions of thecodeword by parity interleaving performed in accordance with theinformation indicating the permutation rule, the bit interleaving methodcomprising: a cyclic block permutation step of applying, using the bitinterleaver, a cyclic block permutation process to a codeword made up ofN cyclic blocks each consisting of Q bits, to reorder the cyclic blocksin accordance with a cyclic block permutation rule defining a reorderingof the cyclic blocks; a bit permutation step of applying, using the bitinterleaver, a bit permutation process to the codeword after the cyclicblock permutation process, to reorder the bits of the codeword inaccordance with a bit permutation rule defining a reordering of thebits; a dividing step of dividing, using the bit interleaver, thecodeword after the bit permutation process into a plurality ofconstellation words, each of the constellation words being made up of Mbits; a modulating step of mapping, using the bit interleaver, eachconstellation word to a modulated signal; and a transmitting step oftransmitting, using the bit interleaver, the transmission signalincluding the modulated signal, wherein N is not a multiple of M, thebit permutation rule defines the reordering of the bits of the codewordafter the cyclic block permutation process, such that the Q bits in eachof N′=N−X cyclic blocks of the N cyclic blocks are each allocated to abit of an identical bit index in Q constellation words and the Qconstellation words are each made up of one bit in each of M cyclicblocks and such that one or more of the N cyclic blocks are excluded andinterleaving is performed only to cyclic blocks remaining, the M cyclicblocks being common to the Q constellation words, where X is a remainderof N divided by M, and a bit index of the bit in each of the Qconstellation words to which the bits in each of the N′=N−X cyclicblocks are each allocated is determined in accordance with the cyclicblock permutation rule.
 2. A bit interleaver for transmitting atransmission signal generated from bits of a codeword, the codewordbeing generated by using a repeat-accumulate quasi-cyclic low-densityparity check coding scheme, the bit interleaver including anon-transitory memory storing information indicating a permutation ruleand circuitry that reorders parity portions of the codeword by parityinterleaving performed in accordance with the information indicating thepermutation rule, the bit interleaver comprising: a cyclic blockpermutator that, in operation, applies a cyclic block permutationprocess to a codeword made up of N cyclic blocks each consisting of Qbits, to reorder the cyclic blocks in accordance with a cyclic blockpermutation rule defining a reordering of the cyclic blocks; and a bitpermutator that, in operation, applies a bit permutation process to thecodeword after the cyclic block permutation process, to reorder the bitsof the codeword in accordance with a bit permutation rule defining areordering of the bits; a divider that, in operation, divides thecodeword after the bit permutation process into a plurality ofconstellation words, each of the constellation words being made up of Mbits; a mapper that, in operation, maps each constellation word to amodulated signal; and a transmitter that, in operation, transmits thetransmission signal including the modulated signals, wherein N is not amultiple of M, the bit permutation rule defines the reordering of thebits of the codeword after the cyclic block permutation process, suchthat the Q bits in each of N′=N−X cyclic blocks of the N cyclic blocksare each allocated to a bit of an identical bit index in Q constellationwords and the Q constellation words are each made up of one bit in eachof M cyclic blocks and such that one or more of the N cyclic blocks areexcluded and interleaving is performed only to cyclic blocks remaining,the M cyclic blocks being common to the Q constellation words, where Xis a remainder of N divided by M, and a bit index of the bit in each ofthe Q constellation words to which the bits in each of the N′=N−X cyclicblocks are each allocated is determined in accordance with the cyclicblock permutation rule.
 3. A receiving method performed by a signalprocessor for receiving a transmission signal transmitted by atransmitting apparatus, the signal processor including a non-transitorymemory storing information indicating a permutation rule and circuitythat performs signal processing on the transmission signal received inaccordance with the information indicating a permutation rule, thetransmission signal including modulated signals generated by mappingeach of N×Q/M constellation words to a modulated signal, each of theconstellation words being made up of M bits and being generated bydividing bits of a codeword to which a bit reordering process has beenapplied, the codeword being generated by using a repeat-accumulatequasi-cyclic low-density parity check coding scheme, parity portions ofthe codeword having been reordered by parity interleaving, the codewordbeing made up of N cyclic blocks each including Q bits, the bitreordering process comprising: a cyclic block permutation process ofreordering the cyclic blocks of the codeword in accordance with a cyclicblock permutation rule defining a reordering of the cyclic blocks; and abit permutation process of reordering the bits of the codeword after thecyclic block permutation process in accordance with a bit permutationrule defining a reordering of the bits, wherein N is not a multiple ofM, the bit permutation rule defines the reordering of the bits of thecodeword after the cyclic block permutation process, such that the Qbits in each of N′=N−X cyclic blocks of the N cyclic blocks are eachallocated to a bit of an identical bit index in Q constellation wordsand the Q constellation words are each made up of one bit in each of Mcyclic blocks and such that one or more of the N cyclic blocks areexcluded and interleaving is performed only to cyclic blocks remaining,the M cyclic blocks being common to the Q constellation words, where Xis a remainder of N divided by M, and a bit index of the bit in each ofthe Q constellation words to which the bits in each of the N′=N−X cyclicblocks are each allocated is determined in accordance with the cyclicblock permutation rule, the signal processing method comprising: areceiving step of receiving, using the signal processor, a receptionsignal acquired by receiving the transmission signal, a demodulatingstep of generating, using the signal processor, a demodulated signal bydemodulating the reception signal; and a decoding step of decoding,using the signal processor, the demodulated signal in accordance withthe cyclic block permutation rule and the bit permutation rule togenerate data before coding according to the quasi-cyclic low-densityparity check coding scheme.
 4. A signal processor for receiving atransmission signal transmitted by a transmitting apparatus, thetransmission signal including modulated signals generated by mappingeach of N×Q/M constellation words to a modulated signal, each of theconstellation words being made up of M bits and being generated bydividing bits of a codeword to which a bit reordering process has beenapplied, the codeword generated by using a repeat-accumulatequasi-cyclic low-density parity check coding scheme, parity portions ofthe codeword having been reordered by parity interleaving, the codewordbeing made up of N cyclic blocks each including Q bits, the bitreordering process comprising: a cyclic block permutation process ofreordering the cyclic blocks of the codeword in accordance with a cyclicblock permutation rule defining a reordering of the cyclic blocks; and abit permutation process of reordering the bits of the codeword after thecyclic block permutation process in accordance with a bit permutationrule defining a reordering of the bits, wherein N is not a multiple ofM, the bit permutation rule defines the reordering of the bits of thecodeword after the cyclic block permutation process, such that the Qbits in each of the N′=N−X cyclic blocks are each allocated to a bit ofan identical bit index in Q constellation words and the Q constellationwords are each made up of one bit in each of M cyclic blocks and suchthat one or more of the N cyclic blocks are excluded and interleaving isperformed only to cyclic blocks remaining, the M cyclic blocks beingcommon to the Q constellation words, where X is a remainder of N dividedby M, and a bit index of the bit in each of the Q constellation words towhich the bits in each of the N′=N−X cyclic blocks are each allocated isdetermined in accordance with the cyclic block permutation rule, thesignal processor comprising: a non-transitory memory storing informationindicating a permutation rule, and circuitry that, in accordance withthe information indicating the permutation rule, operates as: a receiverthat, in operation, receives a reception signal acquired by receivingthe transmission signal, a demodulator that, in operation, generates ademodulated signal by demodulating the reception signal; and a decoderthat, in operation, decodes the demodulated signal in accordance withthe cyclic block permutation rule and the bit permutation rule togenerate data before coding according to the quasi-cyclic low-densityparity check coding scheme.